Digital IC Design

News and Notes

The exam of June 26th will be in the 17th floor meeting room, 17.150.

About the Course

This course will present a broad yet thorough overview of the subject of digital VLSI design, spanning both the circuit and the system abstractions. This complete picture is the only way to make the right tradeoffs, find the most suitable optimizations and the best implementation strategies for very large scale integrated circuits in deep-submicron technologies. After an introduction to technology, devices and interconnect, combinational logic gates and sequential elements are studied. This is followed by system level perspectives of implementation fabrics, interconnect issues, timing issues and the design of macro blocks. At each level, the opportunities and limitations of the physical implementation are considered for finding better solutions and tradeoffs. This includes the consequences of the analog behavior of digital systems with respect to e.g. cross-talk noise and signal waveforms, that generally tend to become more influential with each new technology generation.

The course will include a design project, using Cadence. The grade will be determined for 50% by the exam, and for 50% by the lab course (project) results. In addition, there will be bonus points to be awarded for the best designs. Details will be presented later.

Exam - Material to be studied

A written exam will be held on April 2nd, 2009, from 9 am to 12 am.

The exam will be an open-book exam. You are allowed to have the Rabaey book with you. In addition, you may use a printed copy of the lecture slides, possibly with your own annotations. You are not allowed to consult any other material during the exam.

The following presents the subject material to be studied:

Chapter	Topic	Remarks
Ch 1	Intro	Completely, pay attention to § 1.3
Ch 2	Manufacturing	Only § 2.1 - 2.3
Ch 3	Devices	Completely
Ch 4	Interconnect	Except § 4.4.5, § 4.5
Ch 5	Inverter	Completely
Ch 6	Combinational	Only § 6.1, § 6.2
Ch 7	Sequential	Only § 7.1, § 7.2, § 7.5 (not § 7.5.2)
Ch 10	Timing	Only § 10.1 - 10.3

Assignments Due

A hardopy, color-printed version of the handout for the assigments can be obtained from Mrs. Laura Bruns, room 17.100. It is here for download.
Also see the ppt slides
The assignments need to be completed, but will not be graded. A serious attempt counts as a pass. Please report to Qin for checking your completed assignment. We will try and give you useful feedback.
You should work in pairs (teams of 2).
The first assignment is due on Wed Feb 25. The topic is layout design of a PMOS transistor. Instructions are in Section 1, 2 and 3 and the appendix of the handout.
- Draw a PMOS transistor using Virtuoso
- Make sure it is DRC correct using Calibre
The second assignment is due on Wed Mar 3. The topic is inverter pull-up/pull-down ratio and schematic driven layout. The instructions are in Section 4 of the handout.
- Design a symmetrical inverter using Schematic Composer and Spectre Simulation
- Design Layout using Virtuoso Analog Design Environment (Schematic Driven Layout)

Slides

00 about.pdf	Introduction to the course
01 devices.pdf	Devices (Chapter 3)
02 process.pdf	Manufacturing Process
03 interconnect.pdf	Interconnect Modeling
04 inverter.pdf	Inverter: static, dynamic, power, scaling
05 combinational.pdf	Combinational gates
06 sequential.pdf	Sequential elements
07 timing.pdf	Timing Design
spectre intro.pdf	Introduction to Spectre, Home/lab work for Ch. 3, due Feb 16
assignment.pdf	Assignments due Feb 25 and Mar 3
project.pdf	Description of Project and Grading Policy

Unix and Cadence Practice

MSc Lab

You can use the computers in the MSc lab on the 16th floor of the EWI building (opposite of the elevators, room 16.100 and 16.110). The doors have a code lock, you get the code in class. You can login to these machines with your NetID, and Cadence is available. The machines only run Linux. The lab will be done in pairs, please be careful that you have a good understanding between each other about where (in which of the two accounts) the important design data will be stored, and that you can share data and work.

Linux Getting Started

If you are not yet familiar with Linux, the first thing to do is to make make yourself familiar with the Linux operating system See LinuxStart. The Cadence system (and many other IC design tools, but in fact many other scientific and engineering tools), require a certain level of Linux/Unix skills.

Spectre Getting Started

First, you should work through Chapter 2 of the Spectre User Manual (for simulation). This manual can be found via the Cadence Local Guide. Tips for working through this manual can be found in SpectreIntro. Here you will also find an example of solving Exercise 3.11 from the book exercises (available on the Rabaey site). It also points to a suitable model file.

Documentation

Linux documentation, including how to start for beginners, is collected in LinuxStart.
A Cadence Local Guide provides the details for the local installation of Cadence that we will be using for the Et4293 course. Please know this document before beginning with Cadence. It also contains instructions of where and how to find and open the Cadence documentation.
Information on running Cadence is widely available on the internet. Cdsdoc provides some links.
Local information on IC Design, Tools, Technologies, etc. in general, not tailored to the Et4293 course in general, can be found here