Airborne data collection on resilient system architectures (Adacorsa)

Distributed Artificial Intelligent Systems (DAIS)

Automotive Intelligence for/at Connected Shared Mobility (AI4CSM)

We conduct highly interdisciplinary research involving the fields of mixed-signal VLSI design, computational neuroscience, reconfigurable systems-on-chip, statistical low-power design, and non-linear dynamics.

Low-power neuro-inspired or neuromorphic circuits and algorithms

With the trend of increasing data being collected from myriads of sensors in the age of Internet of Things, it is increasingly more important to find methods to deal with the data as early as possible. Therefore, our prime interest is to extract information or patterns from the data which lead to insights and potential actions based on those insights. We take inspiration from one of the best known low-power pattern recognizers in the world--our brain!

Research topics are:

  • Multi-chip neuron network for cognitive systems realization of digital VLSI for massive scale biophysically accurate neuron simulation.
  • Neuromorphic or neuro-inspired network stochastics, structural plasticity and concurrent processing; development of control methodology for high data throughput.
  • Neuromorphic learning machines development of effective computation algorithms for spiking neural networks based on: extreme learning machine, support vector machine, liquid state machine or echo state networks.

Low-power circuits and systems for neural interfacing

Acquiring signals from the brain is extremely important for understanding brain function and providing potential cure for brain diseases and abnormal function (e.g. epilepsy, tremor). We focus on neural signal recording from implants in the brain. These systems need to record uV level signals from hundreds of electrodes in parallel while dissipating minimal power (to avoid tissue damage).

Research topics are:

  • Brain-machine interfaces modelling and power-per-area efficient implementation of multi-channel time-multiplexed neural interface.
  • Sensing method for implantable neural recordings in secure wireless networks sensing/detection, security, compression and reconstruction of signal spikes originated in implantable neural recording devices (such as multi-electrode arrays) used to monitor the neural action potentials of a designated brain area.
  • Conversion of heterogeneous bio-signals development of conversion based sensing protocol for the joint acquisition of signals in a typical body sensor network composed of different kinds of sensing devices.


Integrated, Fail-Operational, Cognitive Perception, Planning and Control Systems for Highly Automated Vehicles (NewControl)

Programmable Systems for Intelligence in Automobiles (PRYSTINE)

PRYSTINE will deliver (a) fail-operational sensor-fusion framework on component level, (b) dependable embedded E/E architectures, and (c) safety compliant integration of Artificial Intelligence (AI) approaches for object recognition, scene understanding, and decision making within automotive applications.
RESIST: Design approach for resilient integrated electronic systems in automotive and avionics applications
Electronic systems in cars and planes are becoming more sophisticated, and demand more integration and higher performance from semiconductors. However, it is well-recognized that technology scaling alone threatens the integration of highly reliable and safety critical products in scaled technologies due to the associated product lifetime degradation. Hence, this motivates the need for new reliability aware design approaches and solutions. The RESIST project targets reliability aware design methods and run-time adaptive approaches for next-generation resilient integrated electronic systems in Automotive and Avionics. The focus is on reliability, cost-effectiveness and quality of semiconductor devices. The consortium consists of semiconductor companies, SMEs, academia, institutes, and end users. Expected benefits are &>2x more cost-effective resilience solutions, &&>25years lifetime of embedded devices, &>20% higher component/integration density at the same level of reliability, and up to 30% reduced reliability testing costs. An early-warning system by health monitoring of system components will be developed.
COBRA: Computing Fabric for high performance Applications [2010-2014]

Hardwired SoC architectures suffer from a lack of flexibility regarding market evolution, resulting in an excessive design cycle time and increased cost. Furthermore, process variability is not yet well addressed for 32 nm and beyond. The objective of COBRA is to develop and experiment an open, flexible and high performance platform by substituting heterogeneous hardware/software sub-systems by a regular array of processors. The platform will be driven by Telecom, Video and Multimedia benchmark applications and demonstrated on 32nm silicon with 3D stacking.

The objective of COBRA is to develop and experiment an open, flexible and high performance platform by substituting heterogeneous mixed HW/SW specialized sub-systems by an application specific processor array. This massively parallel computing fabric will also improve manufacturability and energy efficiency of new Systems On Chip, due to its design regularity, while at the same time maximising flexibility by allowing software product derivatives to be generated. Software product derivatives will reduce development and manufacturing costs as well as Time-to-market when compared with hardwired alternatives.


CATRENE (CA701) H-INCEPTION Heterogeneous Inception [2014-2015]
New types of emerging applications require microelectronics which closely interact with the surrounding environment in different physical domains (optical, mechanical, acoustical, biological, etc.). The main challenge is to correctly specify, dimension and verify these multi-domain microelectronics assisted systems, to avoid unnecessary errors and redesigns which hamper product quality and thus time to market. Heterogeneous INCEPTION (H-INCEPTION) aims at developing and deploying a novel unified design methodology and tools to address the system-level design and verification need for these systems. This will be deployed inside the European Industry with an ecosystem, delivering all design technology ingredients, from design and verification methodology to the essential modeling languages and simulation engines. H-INCEPTION will enable the industrial partners to create multi-domain virtual prototypes by introducing abstract modeling techniques and fast system simulation concepts. A rich consortium from 5 countries composed of semiconductor and fabless companies, equipment suppliers, EDA vendors, research institutes and universities cover different fields and applications domains such as automotive, wireless, avionics and biomedical will all contribute to the creation and validation of this unified design methodology and ecosystem.


FASTCOM: Fast wireless network for sensor communication within a lithography machine [2010-2013]
Fast wireless network for sensor communication within a lithography machine [2010-2013] Lithography machines have a fast-moving waferstage; also the mask is moving. These stages have many sensors used for accurate positioning. It is desired to connect these sensors wirelessly to a central controller. However, the aggregate data rate is very high (over 1 Gbps), and the latency requirements are very tight. Currently, there are no wireless standards that can accomodate this.


BDREAMS: Beyond DREAMS (Development of a Virtual Prototyping Environment for multi-radio and cognitive radio) [2009-2011]

Beyond DREAMS will provide methods to handle the complexity and shorten the path from specification to implementation of future analogue mixed signal Systems on Chip / Systems in Packages / Hardware / Software and in heterogeneous systems (mechanical, optical, etc.). Extensions for AMS modelling and simulation will be issued in the SoC domain standards: SystemC and IP-XACT via the Standardization bodies OSCI and ACCELLERA. Demonstrators based on industrial test cases will be developed. Consortium is rich of leaders in AMS design domain: three semiconductor companies, a major equipment supplier, research institutes and universities.

Upcoming products of Europe's semiconductor companies more and more interact directly with their analogue physical environment. This leads to a new quality of System on Chip (SoC) and System in Package (SiP) products that combine digital Hardware and software (HW/SW) systems with analogue and mixed-signal blocks such as radio frequency (RF) interfaces, power electronics, or sensors and actuators. In such SoC or SiP, HW/SW systems, often implemented using intellectual property (IP) cores and complex software systems, are tightly interwoven with analogue (RF, power ...) modules. We call such systems Embedded Analogue and Mixed-Signal Systems (EAMS) to underline the new and common complexity that arises by mixing digital HW/SW systems with analogue/RF systems in a SoC or SiP. A common challenge for the development of EAMS is to cope with the digital HW/SW system, and at the same time to understand its environment (e.g. network protocol, traffic, sensor, RF circuits).


MARLOW [EU IST Network of Excellence, 2002-2005]

This EU IST cluster project is the follow-up of TARDIS, and will create a flexible and dynamic framework that will favor the exchange of information and the transfer of technology among the partners and with industry and SMEs. Services that will be provided include, but are not limited to a comprehensive low-power design WEB-portal, a technology and methodology roadmap giving directions for future challenging areas of research and development, on-demand consulting and points of technical synchronization for the low-power design community.


TARDIS [EU IST cluster project, 1997-2002]
This was a European cluster project (for dissemination of research results) with 50 parters from industry and universities, of which we carry the coordination. It is aimed at fostering excellence in microelectronics design skills, and bringing those skills to broad industrial use. It consists of sub-clusters for Low Power Design (LPD: design methods for reducing the power consumption of electronic circuits) and Mixed Signal Design (MSD: design methods for solving problems related to the integration of analog and digital functions on a single semiconductor device).


ESDLPD [1997 - 2001] - Project Coordinator (of 19 projects!)
The 'ESD-LPD: Technical Coordination and Dissemination' is a 'Concerted Action' in the framework of the Esprit ESD-LPD (LowPower and Mixed Signal Design) cluster. The design cluster aims at the further development and broad industrial introduction of Low Power and Mixed Signal Design skills. The objectives are to foster excellence in design skills, and to bring these skills to broad industrial use. The specific goal of the Design cluster is the exploration, demonstration and practical use of design methodologies that lead to a significant relative decrease in power consumption of electronic circuits. The ESD-LPD cluster consists of a coordinated set of design experiments comprising Research, Demonstration and Best Practice ('RDP') work. Beyond their RDP work, the participants of a design experiment are expected to contribute effectively to the Information Capturing and Dissemination ('ICD') work. ICD include those activities that aim primarily at dissemination of design knowledge and experiences to third parties.


JCF Jessi Common Frame [1991-1995] - Management board member
JCF aims to provide integration technology for product engineering, system design automation, manufacturing and
administration. It will integrate a documentation and information system by coupling a homogeneous, easy-to-use, concurrent
engineering platform with the flexibility and sophistication of tools required. JCF is a software infrastructure, or framework,
which serves to configure, execute and manage complex multi- user/multi-platform projects. The framework supports all stages
of the production process, from design definition through product release.