dr. G. Garcea

PhD thesis (Jun 2005): Trade-offs in Buffer Planning
Promotor: R.H.J.M. Otten, Nick van der Meijs

Expertise: IC design verification

Themes: VLSI design verification

Giuseppe Garcea was a PhD student at CAS. He finished in 2005, after which he went to Magma Design Automation.

Trade-offs in buffer planning
G. Garcea;
PhD thesis, TU Delft, Dept. EEMCS, June 2005. ISBN 90-809648-3-2.
document
Statistically aware buffer planning
G.S. Garcea; N.P. van der Meijs; K.J. van der Kolk; R.H.M.J. Otten;
In DATE'04,
Paris, pp. 1402-1403, February 2004.
document
Throughput driven unidirectional bus design for NoC applications
G. Garcea; N.P. van der Meijs;
In Prorisc'04,
Veldhoven, November 2004.
Are Wires Plannable?
G. S. Garcea; R. H. J. M. Otten;
In Proc. Int. Workshop on System-Level Interconnect Prediction,
Sonoma, California, pp. 59--66, March 2001.
document
Assessment of 3D Interconnect Geometry at the System Level
G. S. Garcea; N. P. van der Meijs;
In ProRISC IEEE 12th Annual Workshop on Circuits, Systems and Signal Processing,
pp. 361--365, November 2001.
document
Derivation of Dataflow Networks for a Domain Specific Applications
G. Garcea;
In Proc. of the 1999 IEEE International Symposium on Industrial Electronics,
Bled, Slovenia, July 1999. Part of the student forum on Industrial Electronics within ISIE99.

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Last updated: 8 Nov 2014

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