MSc thesis project proposal

[2022] Ultralow-power GPS Receiver Digital Baseband with a Custom RISC-V Core

Digital circuits and microprocessors play important roles in all electronic devices. While some applications require digital systems to achieve high computation capability with low latency, many other applications require well-balanced digital systems consuming ultra-low power when they are employed in Internet-of-Things (IoT) sensors, biomedical implants, wearable devices, etc.

Global positioning system (GPS) is a global navigation system implemented in most of smartphone and personal electronics. GPS provides us the location, moving speed and an ultra-accurate time (synchronized to the atomic clock used in GPS system). However, for most cases, the GPS chip draws energy dramatically fast while we may not really need the full power of the GPS receiver, e.g., slower refreshing rate and lower positioning accuracy for IoT and wearable applications. In these scenarios, ultralow power consumption matters more than the refreshing rate and accuracy to achieve longer battery life, or even make the system self-sustained with energy harvesting technologies.

In this project, we are design a GPS digital baseband integrated with a RISC-V core for real-time positioning and/or time-synchronization services. We will proposed a novel digital baseband architecture with adaptive satellite acquisition and tracking engines, which consumes ultralow power when the receiver is searching for satellites and after a number of satellites are locked in phase, doppler frequency and delay. In order to make the full use of the open-source RISC-V processor, we are going to use Chisel as the design language, which is very similar to Verilog or VHDL [1]. The description about Chisel is given below:

About Chisel:

While most of current digital circuits are designed in Verilog or VHDL, all digital designs in this project will be written in Chisel [1]. Instead of building the digital hardware directly, we will use Chisel to build a highly parameterized digital hardware generator. Chisel is a hardware construction language, which is very easy to learn with entry-level digital IC design background. If you have used VHDL or Verilog to design a finite state machine (FSM), then you have the sufficient prerequisite and are ready to go. For a new Chisel learner, it only takes 1-2 weeks to go through the bootcamp and tutorial, and you will be ready to start designing your first Chisel circuit. Chisel allows designers to build a hardware in much less time and the Chisel generator can generate different flavors of hardware according to applications. Designers can use Chisel to implement highly customized RISC-V processors easily and the entire Chisel ecosystem is open-source. Chisel and the Chisel-based digital design methodology are drawing more and more industrial interests and have been employed for designing digital systems in several world-leading companies, e.g., Tensor Processing Unit (TPU) by Google.

[1] Chisel: Constructing Hardware in a Scala Embedded Language. URL:


1. Get familiar with Chisel hardware construction language and literature review of GPS receiver architecture and RISC-V microprocessor.
2. Design the GPS receiver digital baseband and RISC-V system with Chisel.
3. Integrate the system to meet performance and power requirements. The system should achieve fast satellite signal acquisition and ultralow power consumption after satellite signals are locked.


You should have basic VHDL/Verilog digital design experience (e.g. having designed a finite state machine with VHDL or Verilog). Prior experience or knowledge on Chisel is not required. You will be able to master Chisel withing 1-2 weeks after you start. If you are interested, please send your CV, BSc transcripts and MSc grades (obtained to date) to Sijun Du at email:


dr. Sijun Du

Electronic Instrumentation Group

Department of Microelectronics

Last modified: 2022-12-29