Broadband analog delay filter and amplifier (NXP)

Multi-standard receivers targeting wideband signal conversion (BW >100MHz) require power efficient data converters which can maintain linearity in the presence of strong blockers. Although a continuous-time oversampling pipelined data converter can achieve BWs greater than 1GHz but it dissipates more 1W [1]. Recently, it has been demonstrated that a SAR-assisted continuous-time pipelined data converter achieved a signal BW greater than 40MHz with only 3.2mW of power dissipation [2]. However, a CT pipelined ADC architecture requires that the delay of the coarse conversion phase must be compensated by a broadband analog filter. This thesis focuses on the implementation of a broadband analog filter which can achieve constant group delay. The amplifier will be integrated as a part of a broadband oversampled data-converter.

In this master thesis project you will do/learn:

• In depth study of ADC (or DAC) architecture
• Design of analog and mixed-signal circuits in 28nm CMOS
• Circuit simulations with Spectre (or other simulator)
• Layout design of circuits and simulation of extracted layout
• Build understanding of impact of process imperfections and parasitic artifacts on performance

Ref:
[1] H. Shibata et al., “A 9-GS/s 1.125-GHz BW Oversampling Continuous-Time Pipeline ADC Achieving −164-dBFS/Hz NSD,” IEEE Journal of Solid-State Circuits, vol. 52, no. 12, pp. 3219–3234, Dec. 2017.
[2] P. Cenci et al., “A 3.2mW SAR-assisted CTΔΣ ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS,” in 2019 Symposium on VLSI Circuits, Jun. 2019, pp. C230–C231.

Assignment

In this master thesis project you will do/learn

• In depth study of ADC (or DAC) architecture
• Design of analog and mixed-signal circuits in 28nm CMOS
• Circuit simulations with Spectre (or other simulator)
• Layout design of circuits and simulation of extracted layout
• Build understanding of impact of process imperfections and parasitic artifacts on performance

A stipend is provided.

Requirements

• Good knowledge of analog and mixed circuit design.
• Good understanding of Data Converters.
• Familiarity with Matlab and Cadence.
• You will be collaborating with researchers from NXP Semiconductors so good communication and presentation skills are essential.

Contact

dr.ir. Muhammed Bolatkale

Electronic Instrumentation Group

Department of Microelectronics

Last modified: 2021-02-10