Agenda
Signal Processing Seminar
- Thursday, 14 December 2023
- 11:00-12:00
- HB 17.140
Error-correcting codes and cryptography: from theory to practice
Xinmiao ZhangOhio State University
Error-correcting codes (ECCs) and cryptography schemes are indispensable to the reliability and security of numerous classic and emerging systems. Advanced ECCs play essential roles in the performance of 5G/6G wireless communications, hyper-scale distributed storage, in/near-memory computing, and quantum computing. They are also key enablers of high-density next-generation memories and wafer-scale integration, which are important pillars of the CHIPS Act. With the development of new technologies, such as quantum computers and cloud computing, traditional cryptography schemes are no longer secure and/or pose privacy concerns. There are imminent needs for post-quantum cryptography and homomorphic encryption for privacy-preserving cloud computing. Protecting the circuit chips implementing advanced functions from counterfeiting is also necessary to preserve the semiconductor supremacy achieved by the CHIPS Act.
This talk presents our recent contributions on related topics. Efficient and high-speed generalized integrated interleaved ECC decoders are developed to meet the tight latency and excellent error-correcting capability requirements of next-generation hyper-speed memories. Code construction and decoder designs are jointly optimized to enable low-latency failure recovery and continued scaling of distributed storage. Our generalized logic locking includes many previous designs as special cases and achieves better resilience towards various attacks. Logic locking that can effectively protect chips implementing fault-tolerant functions, such as machine learning, are also developed by exploiting algorithmic specifics. Last by not least, high-speed and low-complexity hardware accelerators are designed for homomorphic encryption and post-quantum cryptography.
Biography
Xinmiao Zhang received her Ph.D. degree in Electrical Engineering from the University of Minnesota. She is currently a Professor at the Ohio State University. She was a Senior Technologist at Western Digital/SanDisk 2013-2017. Prior to that, she was a Timothy E. and Allison L. Schroeder Associate Professor at Case Western Reserve University. Prof. Zhang’s research spans the areas of VLSI architecture design, digital storage and communications, cryptography, security, and signal processing.
Prof. Zhang is a recipient of the NSF CAREER Award 2009, the College of Engineering Lumley Research Award at The Ohio State University 2022, the Best Paper Award at ACM Great Lakes Symposium on VLSI 2004, and Best Paper Award at International SanDisk Technology Conference 2016. She authored “VLSI Architectures for Modern Error-Correcting Codes” (CRC Press, 2015), and co-edited “Wireless Security and Cryptography: Specifications and Implementations” (CRC Press, 2007). Prof. Zhang was elected the Vice President-Technical Activities of the IEEE Circuits and Systems Society (CASS) 2022-2023 and served on the Board of Governors of CASS 2019-2021. She was also the Chair (2021-2022) and a Vice-Chair (2017-2020) of the Data Storage Technical Committee (DSTC) of the IEEE Communications Society. She served on the technical program and organization committees of many conferences, including ISCAS, ICC, GLOBECOM, SiPS, GlobalSIP, MWSCAS, and GLSVLSI. She has been an Associate Editor for the IEEE Transactions on Circuits and Systems-I (TCAS-I) 2010-2019 and IEEE Open Journal of Circuits and Systems since 2019. She will be the Associate Editor-in-Chief of TCAS-I 2024-2025.
